Arm® Generic Interrupt Controller Architecture Specification GIC architecture version 3 and version 4
Copyright © 2008, 2011, 2015-2021 Arm Limited or its affiliates. All rights reserved.
Arm Generic Interrupt Controller Architecture Specification GIC architecture version 3 and version 4
Copyright © 2008, 2011, 2015-2021 Arm Limited or its affiliates. All rights reserved.
Release Information
The following changes have been made to this document.
Change History
| Date | Issue | Confidentiality | Change |
|---|---|---|---|
| June 2015 | A | Non-confidential | First release of GICv3 and GICv4 issue A. |
| December 2015 | B | Non-confidential | First release of GICv3 and GICv4 issue B. |
| July 2016 | C | Non-confidential | First release of GICv3 and GICv4 issue C. |
| August 2017 | D | Non-confidential | First release of GICv3 and GICv4 issue D. |
| January 2019 | E | Non-confidential | First release of GICv3 and GICv4 issue E. |
| February 2020 | F | Non-confidential | First release of GICv3 and GICv4.1 issue F. |
| February 2021 | G | Non-confidential | First release of GICv3 and GICv4.1 issue G. |
Some of the information in this specification was previously published in Arm[®] Generic Interrupt Controller, Architecture version 2.0, Architecture Specification .
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Contents Arm Generic Interrupt Controller Architecture Specification GIC architecture version 3 and version 4
| Preface | |||
|---|---|---|---|
| About this specification | |||
| Using this specification | |||
| Conventions | |||
| Additional reading | |||
| Feedback | |||
| Chapter | 1 | Introduction | |
| — | — | — | — |
| 1.1 | About the Generic Interrupt Controller (GIC) | ||
| 1.2 | Terminology | ||
| 1.3 | Supported configurations and compatibility | ||
| Chapter | 2 | Distribution and Routing of Interrupts | |
| 2.1 | The Distributor and Redistributors | ||
| 2.2 | INTIDs | ||
| 2.3 | Affinity routing | ||
| Chapter | 3 | GIC Partitioning | |
| 3.1 | The GIC logical components | ||
| 3.2 | Interrupt bypass support | ||
| Chapter | 4 | Physical Interrupt Handling and Prioritization | |
| 4.1 | Interrupt lifecycle | ||
| 4.2 | Locality-specific Peripheral Interrupts | ||
| 4.3 | Private Peripheral Interrupts | ||
| 4.4 | Software Generated Interrupts | ||
| 4.5 | Shared Peripheral Interrupts | ||
| 4.6 | Interrupt grouping | ||
| 4.7 | Enabling the distribution of interrupts | ||
| 4.8 | Interrupt prioritization | ||
| Chapter | 5 | Locality-specific Peripheral Interrupts and the ITS | |
| 5.1 | LPIs | ||
| 5.2 | The Interrupt Translation Service | ||
| 5.3 | ITS commands | ||
| 5.4 | Common ITS pseudocode functions | ||
| 5.5 | ITS command error encodings | ||
| 5.6 | ITS power management | ||
| Chapter | 6 | Virtual Interrupt Handling and Prioritization | |
| 6.1 | About GIC support for virtualization | ||
| 6.2 | Operation overview | ||
| 6.3 | Configuration and control of VMs | ||
| 6.4 | Pseudocode | ||
| Chapter | 7 | GICv4.0 Virtual LPI Support | |
| 7.1 | About GICv4.0 virtual Locality-specific Peripheral Interrupt support | ||
| 7.2 | Direct injection of virtual interrupts | ||
| Chapter | 8 | GICv4.1 Virtual Interrupt Support | |
| 8.1 | About GICv4.1 virtual interrupt support | ||
| 8.2 | Changes to the CPU interface | ||
| 8.3 | ITS commands | ||
| 8.4 | vPEID width | ||
| 8.5 | Doorbells | ||
| 8.6 | vPE residency and locating data structures | ||
| 8.7 | Register based vLPI invalidation | ||
| 8.8 | Direct injection of vSGIs | ||
| Chapter | 9 | Memory Partitioning and Monitoring | |
| 9.1 | Overview | ||
| 9.2 | MPAM and the Redistributors | ||
| 9.3 | MPAM and the ITS | ||
| 9.4 | GIC usage of MPAM | ||
| 9.5 | GICv4.1 data structures and MPAM | ||
| Chapter | 10 | Connecting to Armv8-R AArch64 PEs | |
| 10.1 | Armv8-R AArch64 CPU interface requirements | ||
| Chapter | 11 | Power Management | |
| 11.1 | Power management | ||
| Chapter | 12 | Programmers’ Model | |
| 12.1 | About the programmers’ model | ||
| 12.2 | AArch64 System register descriptions | ||
| 12.3 | AArch64 System register descriptions of the virtual registers | ||
| 12.4 | AArch64 virtualization control System registers | ||
| 12.5 | AArch32 System register descriptions | ||
| 12.6 | AArch32 System register descriptions of the virtual registers | ||
| 12.7 | AArch32 virtualization control System registers | ||
| 12.8 | The GIC Distributor register map | ||
| 12.9 | The GIC Distributor register descriptions | ||
| 12.10 | The GIC Redistributor register map | ||
| 12.11 | The GIC Redistributor register descriptions | ||
| 12.12 | The GIC CPU interface register map | ||
| 12.13 | The GIC CPU interface register descriptions | ||
| 12.14 | The GIC virtual CPU interface register map | ||
| 12.15 | The GIC virtual CPU interface register descriptions | ||
| 12.16 | The GIC virtual interface control register map | ||
| 12.17 | The GIC virtual interface control register descriptions | ||
| 12.18 | The ITS register map | ||
| 12.19 | The ITS register descriptions | ||
| 12.20 | Pseudocode | ||
| Chapter | 13 | System Error Reporting | |
| 13.1 | About System Error reporting | ||
| Chapter | 14 | Legacy Operation and Asymmetric Configurations | |
| 14.1 | Legacy support of interrupts and asymmetric configurations | ||
| 14.2 | The asymmetric configuration | ||
| 14.3 | Support for legacy operation of VMs | ||
| Appendix A | GIC Stream Protocol interface | ||
| A.1 | Overview | ||
| A.2 | Signals and the GIC Stream Protocol | ||
| A.3 | The GIC Stream Protocol | ||
| A.4 | Alphabetic list of command and response packet formats | ||
| Appendix B | Pseudocode Definition | ||
| B.1 | About Arm pseudocode | ||
| B.2 | Data types | ||
| B.3 | Expressions | ||
| B.4 | Operators and built-in functions | ||
| B.5 | Statements and program structure | ||
| B.6 | Pseudocode terminology | ||
| B.7 | Miscellaneous helper procedures and support functions |
Glossary
vii viii
Preface
This preface introduces the Arm[®] Generic Interrupt Controller Architecture Specification . It contains the following sections:
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About this specification on page x.
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Using this specification on page xi.
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Conventions on page xiii.
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Additional reading on page xiv.
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Feedback on page xv. Preface About this specification
About this specification
This specification describes the Arm Generic Interrupt Controller (GIC) architecture. It defines versions 3.0, 3.1, 3.2 (GICv3), 4.0, and 4.1 (GICv4) of the GIC architecture.
Throughout this document, references to the GIC or a GIC refer to a device that implements the GIC architecture. Unless the context makes it clear that a reference is to an IMPLEMENTATION DEFINED feature of the device, these references describe the requirements of this specification.
Intended audience
This specification is for users who want to design, implement, or program the GIC in a range of Arm-compliant implementations, from simple uniprocessor implementations to complex multiprocessor systems. It does not assume familiarity with previous versions of the GIC.
The specification assumes that users have some experience of Arm products, and are familiar with the terminology that describes the Armv8 architecture. See the Arm[®] Architecture Reference Manual, Armv8, for Armv8-A architecture profile for more information. Preface Using this specification
Using this specification
This specification is organized into the following chapters:
Chapter 1 Introduction
Read this for an overview of the GIC, and information about the terminology that this document uses.
Chapter 2 Distribution and Routing of Interrupts
Read this for information about how the GIC uses affinity routing to distribute interrupts.
Chapter 3 GIC Partitioning
Read this for an overview of the GIC partitioning and information about the GIC logical components. Chapter 4 Physical Interrupt Handling and Prioritization Read this for information about how the GIC handles physical interrupts. Chapter 5 Locality-specific Peripheral Interrupts and the ITS Read this for a description of Locality-specific Peripheral Interrupts (LPIs) and the use of the Interrupt Translation Service (ITS). Chapter 6 Virtual Interrupt Handling and Prioritization Read this for information about how the GIC handles virtual interrupts. Chapter 7 GICv4.0 Virtual LPI Support
Read this for information about how the GIC handles virtual interrupts. Chapter 8 GICv4.1 Virtual Interrupt Support Read this for information about changes to virtual interrupt support in GICv4.1. Chapter 9 Memory Partitioning and Monitoring Read this for a description of Memory Partitioning and Monitoring in the context of the GIC. Chapter 10 Connecting to Armv8-R AArch64 PEs Read this for information about connecting a GIC to PEs that implement Armv8-R64. Chapter 11 Power Management Read this for information about GIC power management. Chapter 12 Programmers’ Model Read this for a description of the GIC register interfaces, and all GIC registers. Chapter 13 System Error Reporting Read this for information about GIC support for error reporting. Chapter 14 Legacy Operation and Asymmetric Configurations Read this for information about GIC support for legacy operation and asymmetric configurations. Appendix A GIC Stream Protocol interface
Read this for a description of the AXI4-Stream protocol standard message-based interface that the GIC Stream Protocol interface uses.
Appendix B Pseudocode Definition
Read this for a definition of the pseudocode that is used in this specification.
Glossary
Read this for definitions of some of the terms used in this specification. Preface Using this specification
Preface Conventions
Conventions
The following sections describe conventions that this book can use:
-
Typographic conventions .
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Signals .
-
Numbers .
-
Pseudocode descriptions .
Typographic conventions
The typographical conventions are:
italic Introduces special terminology, and denotes citations. bold Denotes signal names, and is used for terms in descriptive lists, where appropriate. monospace Used for assembler syntax descriptions, pseudocode, and source code examples. Also used in the main text for instruction mnemonics and for references to other items appearing in assembler syntax descriptions, pseudocode, and source code examples.
SMALL CAPITALS
Used for a few terms that have specific technical meanings, and are included in the Glossary .
Colored text Indicates a link. This can be:
-
A URL, for example https://developer.arm.com.
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A cross-reference, that includes the page number of the referenced information if it is not on the current page, for example, About the Generic Interrupt Controller (GIC) on page 1-18.
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A link, to a chapter or appendix, or to a glossary entry, or to the section of the document that defines the colored term, for example, Banked register or GICC_CTLR.
Signals
In general this specification does not define processor signals, but it does include some signal examples and recommendations. The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:
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HIGH for active-HIGH signals
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LOW for active-LOW signals.
Lowercase n At the start or end of a signal name denotes an active-LOW signal.
Numbers
Numbers are normally written in decimal. Binary numbers are preceded by 0b, and hexadecimal numbers by 0x. In both cases, the prefix and the associated value are written in a monospace font, for example 0xFFFF0000.
Pseudocode descriptions
This specification uses a form of pseudocode to provide precise descriptions of the specified functionality. This pseudocode is written in a monospace font, and follows the conventions described in the Arm[®] Architecture Reference Manual, Armv8, for Armv8-A architecture profile and the Arm[®] Architecture Reference Manual, Armv7-A and Armv7-R edition . Preface Additional reading
Additional reading
This section lists relevant publications from Arm and third parties.
See Arm Developer, https://developer.arm.com for access to Arm documentation.
Arm publications
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AMBA[®] 4 AXI4-Stream Protocol Specification (ARM IHI 0051).
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Arm[®] Architecture Reference Manual, Armv7-A and Armv7-R edition (ARM DDI 0406).
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Arm[®] Architecture Reference Manual, Armv8, for Armv8-A architecture profile (ARM DDI 0487).
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Arm[®] Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598).
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Arm[®] Generic Interrupt Controller, Architecture version 2.0, Architecture Specification (ARM IHI 0048).
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Arm[®] CoreSight[™] Architecture Specification v3.0 (ARM IHI 0029).
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Arm[®] Server Base System Architecture (SBSA) (ARM-DEN-0029).
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GICv3 and GICv4 Software Overview (DAI 0492).
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• Application Note GIC Stream Protocol Interface (ARM-ECM-0495013).
Other publications
The following books are referred to in this manual, or provide more information:
- JEDEC Solid State Technology Association, Standard Manufacture’s Identification Code , JEP106. Preface Feedback
Feedback
Arm welcomes feedback on its documentation.
Feedback on this manual
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If you have comments on the content of this manual, send an e-mail to errata@arm.com. Provide: • The title.
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The number, Arm IHI 0069G.
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The page numbers to which your comments apply.
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A concise explanation of your comments.
Arm also welcomes general suggestions for additions and improvements. Preface Feedback