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Chapter 11: Power Management

  • This chapter describes power management. It contains the following section:

  • Power management .

11.1 Power management

In an implementation compliant with the GICv3 architecture, the CPU interface and the PE must be in the same power domain, but this does not have to be the same power domain as that within which the associated Redistributor is located. This means that it is possible to have a situation where the PE and its CPU interface are powered down, and the Redistributor, Distributor, and ITS, are powered up. In this situation, the GIC architecture supports the use of interrupts targeted at the PE to signal a powerup event to the PE and CPU interface.

Note Arm strongly recommends that the GIC is not configured in such a way that an interrupt can cause wake-up of a particular PE, if on waking software on that PE cannot handle the interrupt.

GICv3 provides power management to control this situation, because the architecture is designed to allow the Redistributors designed by one organization to be used with PEs and CPU interfaces that have been designed by a different organization.

All other aspects of power management for the GIC are IMPLEMENTATION DEFINED.

Before powering down the CPU interface and the PE when the Redistributor is powered up, software must put the interface between the CPU interface and the Redistributor into the quiescent state or the system will become UNPREDICTABLE. The transition to the quiescent state is initiated by setting GICR_WAKER.ProcessorSleep to 1. When the interface is quiescent, GICR_WAKER.ChildrenAsleep is also set to 1.

GICR_WAKER.ProcessorSleep == 1 has the following effects:

  • The Redistributor does not forward any interrupts for the PE to the CPU interface. If there is a pending interrupt for the PE that would otherwise be forwarded to the PE, a hardware signal, WakeRequest , is asserted to indicate that the PE is to have its power restored. In a GICv4 implementation, this applies to virtual LPIs in addition to any other interrupts.

  • The Distributor does not select this PE as a candidate for selection for a 1 of N interrupt, unless GICD_CTLR.E1NWF == 1, and the PE has been selected by an IMPLEMENTATION DEFINED mechanism:

    • For a 1 of N interrupt that causes wake-up, the GIC is not required to select a new target PE if the PE that received the WakeRequest does not handle the interrupt on waking.

When the interface between the Redistributor and the CPU interface is in a quiescent state, the following architectural state of the CPU interface can be saved as part of saving the state within the power domain of the CPU interface and the PE:

  • The CPU interface state related to physical interrupts of the connected PE.

  • The CPU interface state related to virtual interrupts that is part of the vPE that is scheduled on the associated PE.

Setting GICR_WAKER.ProcessorSleep to 1 when the physical group enables in the CPU interface are set to 1 results in UNPREDICTABLE behavior.

When GICR_WAKER.ProcessorSleep == 1 or GICR_WAKER.ChildrenAsleep == 1 then a write to any GICC_, GICV_, GICH_, ICC_, ICV_, or ICH_ registers, other than those in the following list, is unpredictable:

  • ICC_SRE_EL1.

  • ICC_SRE_EL2.

  • ICC_SRE_EL3.